1. Field of the Invention
The present invention relates to the field of bus protocols in computer systems. More specifically, this invention relates to methods and circuitry for requesting and responding to requests over a bus, for transfers of information during consecutive processor clock cycles.
2. Description of Related Art
Many known computer systems comprise a plurality of modules such as processor modules, memory modules, etc., which communicate over a system bus. Typically, the modules may be under control of a common or synchronized clock signal. Generally such a configuration provides a CPU clock signal on the bus. Individual modules generate signals on the bus synchronous to the CPU clock signal. A deterministic relationship is assumed to exist during the design of the various modules. Modules, such as the processing unit, may then be designed to add a fixed number of wait states to their access cycles to accommodate slower modules. Such a system design more than likely will require changes to the individual modules if the CPU clock speed is increased, for example. Therefore, it is difficult to replace one module in the computer system without affecting other modules.
Known computer systems further typically may utilize a plurality of configuration or "dip" switches. The switches are utilized to provide information to the processor unit regarding the configuration of installed modules. For example, a particular system may be configured with a first memory board having four megabytes of memory and a second memory board having an additional eight megabytes of memory. In this configuration, configuration switches, either on the main system board (motherboard or baseboard) or on the individual add-on modules may be set to indicate that four megabytes of memory are installed on the first memory board and eight megabytes of memory are installed on the second memory board.
In such systems, address decode logic may be employed on each memory board in the system. Based on the setting of the configuration switches in the exemplary system described above, address decode logic may be employed such that the first board addresses memory in system memory space from memory address 0 to memory address 4 million (M)-1 and the second board addresses memory in the system memory space from memory address 4M to memory address 12M-1.
In addition to the varying clock speeds of microprocessors, certain modern high performance microprocessors provide modes wherein data is transferred over a bus during every clock cycle of the microprocessor. Such a transfer is known as a "burst" mode because address information need not be driven by the central processing unit to the memory at every CPU or memory clock cycle. This may be useful if an entire block of contiguous data is required. The microprocessor may request a transfer of a "block" or contiguous locations of data versus a transferring individual words of data. Typically, lower-performance microprocessors transfer data by driving address information alternated with data information on the bus. This causes a delay in accessing data if consecutive addresses of memory are required by the processor. Another limitation of synchronous state of the art bus architectures is that they do not provide means for transferring data on consecutive bus cycles as required by modern high-performance central processing units (CPU's).